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A radiation tolerant clock generator for the CMS endcap timing layer readout chip

Journal Article · · Journal of Instrumentation
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  1. Central China Normal Univ., Wuhan (China); Southern Methodist Univ., Dallas, TX (United States)
  2. Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States)
  3. European Organization for Nuclear Research (CERN), Geneva (Switzerland); Katholieke Univ. Leuven, Heverlee (Belgium)
  4. European Organization for Nuclear Research (CERN), Geneva (Switzerland)
  5. Southern Methodist Univ., Dallas, TX (United States)
  6. Central China Normal Univ., Wuhan (China)
  7. Katholieke Univ. Leuven, Heverlee (Belgium)
+ Show Author Affiliations

Here, we present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear Energy Transfer (LET) from 1.3 to 62.5 MeV × cm2/mg.

Research Organization:
Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States)
Sponsoring Organization:
USDOE Office of Science (SC), High Energy Physics (HEP)
Grant/Contract Number:
AC02-07CH11359
OSTI ID:
1833278
Report Number(s):
FERMILAB-CONF--21-633-PPD; arXiv:2110.12625; oai:inspirehep.net:1951076
Journal Information:
Journal of Instrumentation, Journal Name: Journal of Instrumentation Journal Issue: 03 Vol. 17; ISSN 1748-0221
Publisher:
Institute of Physics (IOP)Copyright Statement
Country of Publication:
United States
Language:
English

References (3)

A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit With High Speed Feed Forward Correction in 65 nm CMOS journal May 2020
A 2.56-GHz SEU Radiation Hard $LC$ -Tank VCO for High-Speed Communication Links in 65-nm CMOS Technology journal January 2018
The lpGBT PLL and CDR Architecture, Performance and SEE Robustness conference March 2020

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Related Subjects

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS
Front-end electronics for detector readout
Radiation-hard electronics
VLSI circuits