An FPGA-based readout chip emulator for the CMS ETL detector upgrade
Journal Article
·
· Journal of Instrumentation
- Southern Methodist Univ., Dallas, TX (United States)
- Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States)
- Univ. of Illinois, Chicago, IL (United States)
Here, we present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.
- Research Organization:
- Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC), High Energy Physics (HEP)
- Grant/Contract Number:
- AC02-07CH11359
- OSTI ID:
- 1958481
- Report Number(s):
- FERMILAB-PUB--23-056-PPD; arXiv:2302.01548; oai:inspirehep.net:2629514
- Journal Information:
- Journal of Instrumentation, Journal Name: Journal of Instrumentation Journal Issue: 02 Vol. 18; ISSN 1748-0221
- Publisher:
- Institute of Physics (IOP)Copyright Statement
- Country of Publication:
- United States
- Language:
- English
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