A high-resolution clock phase shifter circuitry for ALTIROC
Journal Article
·
· Journal of Instrumentation
Abstract
A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of 97.7 ps and an adjustable range of 25 ns. The fine delay unit is based on a Delay Locked Loop (DLL) operating at 640 MHz. The phase shifter is fabricated in a 130 nm CMOS process. The area of the phase shifter is 725 µm × 248 µm. The Differential Non-Linearity (DNL) and the Integral Non-Linearity (INL) are ±0.6 LSB and ±0.75 LSB, respectively. The jitter from −25 °C to 20 °C is less than 15.5 ps (RMS), including the contributions from the FPGA clock source and the PLL. The power consumption is 11.2 mW.
- Research Organization:
- Southern Methodist Univ., Dallas, TX (United States)
- Sponsoring Organization:
- USDOE
- OSTI ID:
- 2424822
- Journal Information:
- Journal of Instrumentation, Journal Name: Journal of Instrumentation Journal Issue: 01 Vol. 18; ISSN 1748-0221
- Publisher:
- Institute of Physics (IOP)
- Country of Publication:
- United States
- Language:
- English
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