Three dimensional vertically structured electronic devices

Conway, Adam; Harrison, Sara Elizabeth; Nikolic, Rebecca; Shao, Qinghui; Voss, Lars

Three dimensional vertically structured electronic devices

Patent · Tue Dec 17 04:00:00 EST 2024

OSTI ID:2542925

Conway, Adam; Harrison, Sara Elizabeth; Nikolic, Rebecca; Shao, Qinghui; Voss, Lars

An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.

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Research Organization:: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Organization:: USDOE

DOE Contract Number:: AC52-07NA27344

Assignee:: Lawrence Livermore National Security, LLC (Livermore, CA)

Patent Number(s):: 12,170,330

Application Number:: 17/238,012

OSTI ID:: 2542925

Country of Publication:: United States

Language:: English

References (15)

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