Three dimensional vertically structured electronic devices

Patent · Tue Aug 29 04:00:00 EDT 2023

OSTI ID:2222239

Conway, Adam; Harrison, Sara Elizabeth; Nikolic, Rebecca; Shao, Qinghui; Voss, Lars

In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC52-07NA27344
• Assignee: Lawrence Livermore National Security, LLC (Livermore, CA)
• Patent Number(s): 11,742,424
• Application Number: 17/143,972
• OSTI ID: 2222239
• Country of Publication: United States
• Language: English