Three dimensional vertically structured electronic devices

Patent · Tue Jun 01 04:00:00 EDT 2021

OSTI ID:1824032

Conway, Adam; Harrison, Sara Elizabeth; Nikolic, Rebecca J.; Shao, Qinghui; Voss, Lars

In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC52-07NA27344
• Assignee: Lawrence Livermore National Security, LLC (Livermore, CA)
• Patent Number(s): 11,024,734
• Application Number: 15/398,652
• OSTI ID: 1824032
• Country of Publication: United States
• Language: English