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Soft error-mitigating semiconductor design system and associated methods

Patent ·
OSTI ID:2542088
; ;
A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device. The resultant layout generated from the TMR configuration may relax constraints imposed on register transfer level (RTL) engineers to make rad-hard designs, as automation introduces TMR storage registers, memory element spacing, and clock delay/triplication with minimal designer input.
Research Organization:
Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC02-07CH11359
Assignee:
Fermi Research Alliance, LLC (Batavia, IL)
Patent Number(s):
11,966,676
Application Number:
18/103,970
OSTI ID:
2542088
Country of Publication:
United States
Language:
English

References (2)

Characterization of Soft Error Rate Against Memory Elements Spacing and Clock Skew in a Logic with Triple Modular Redundancy in a 65nm Process
  • Miryala, Sandeep; Hemperek, Tomasz; Menouni, Mohsine
  • Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018) https://doi.org/10.22323/1.343.0029
conference May 2019
On-Chip Characterization of Single-Event Transient Pulsewidths journal December 2006

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