Characterization of Soft Error Rate Against Memory Elements Spacing and Clock Skew in a Logic with Triple Modular Redundancy in a 65nm Process

Conference · Mon May 20 04:00:00 EDT 2019 · PoS

DOI:https://doi.org/10.22323/1.343.0029· OSTI ID:1843258

Miryala, Sandeep ^[1]; Hemperek, Tomasz ^[2]; Menouni, Mohsine ^[3]

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1. Fermilab
2. Bonn U.
3. Marseille, CPPM

Single Event Effects introduce soft errors in ASICs. Design methodologies like Triple ModularRedundancy (TMR) with clock skew insertion, a system level redundancy technique is a commonpractice by designers to mitigate soft errors. However, the optimal spacing between memoryelements in a TMR in 65nm process hasn't been addressed so far. RD53SEU is a mini ASICdevelopment under the framework of the CERN RD53 collaboration to characterize the soft errorrates against the separation spacing and clock skew between memory elements in a TMR. Thisarticle describes the architecture and design aspects of the various test structures on the RD53SEUtest chip.

• Research Organization: Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States)
• Sponsoring Organization: USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25)
• DOE Contract Number: AC02-07CH11359
• OSTI ID: 1843258
• Report Number(s): FERMILAB-CONF-19-817-V; oai:inspirehep.net:1747358
• Conference Information: Journal Name: PoS Journal Volume: TWEPP2018
• Country of Publication: United States
• Language: English

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46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY