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Title: Investigation of negative bias temperature instability dependence on fin width of silicon-on-insulator-fin-based field effect transistors

Abstract

The fin width dependence of negative bias temperature instability (NBTI) of double-gate, fin-based p-type Field Effect Transistors (FinFETs) fabricated on silicon-on-insulator (SOI) wafers was investigated. The NBTI degradation increased as the fin width narrowed. To investigate this phenomenon, simulations of pre-stress conditions were employed to determine any differences in gate oxide field, fin band bending, and electric field profile as a function of the fin width. The simulation results were similar at a given gate stress bias, regardless of the fin width, although the threshold voltage was found to increase with decreasing fin width. Thus, the NBTI fin width dependence could not be explained from the pre-stress conditions. Different physics-based degradation models were evaluated using specific fin-based device structures with different biasing schemes to ascertain an appropriate model that best explains the measured NBTI dependence. A plausible cause is an accumulation of electrons that tunnel from the gate during stress into the floating SOI fin body. As the fin narrows, the sidewall device channel moves in closer proximity to the stored electrons, thereby inducing more band bending at the fin/dielectric interface, resulting in a higher electric field and hole concentration in this region during stress, which leads to more degradation.more » The data obtained in this work provide direct experimental proof of the effect of electron accumulation on the threshold voltage stability in FinFETs.« less

Authors:
;  [1];  [2]; ; ;  [3]
  1. Materials Science and Engineering, University of Texas at Dallas, 800 W. Campbell Road, Richardson, Texas 75080 (United States)
  2. Department of Electrical and Computer Enginering, University of Florida, Gainesville, Florida 32611 (United States)
  3. SEMATECH, Albany, New York 12203 (United States)
Publication Date:
OSTI Identifier:
22412963
Resource Type:
Journal Article
Resource Relation:
Journal Name: Journal of Applied Physics; Journal Volume: 117; Journal Issue: 3; Other Information: (c) 2015 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA)
Country of Publication:
United States
Language:
English
Subject:
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SUPERFLUIDITY; CONCENTRATION RATIO; DIELECTRIC MATERIALS; ELECTRIC FIELDS; ELECTRIC POTENTIAL; ELECTRONS; FIELD EFFECT TRANSISTORS; HOLES; INTERFACES; OXIDES; PHASE STABILITY; P-TYPE CONDUCTORS; SILICON; STRESSES

Citation Formats

Young, Chadwin D., E-mail: chadwin.young@utdallas.edu, Wang, Zhe, Neugroschel, Arnost, Majumdar, Kausik, Matthews, Ken, and Hobbs, Chris. Investigation of negative bias temperature instability dependence on fin width of silicon-on-insulator-fin-based field effect transistors. United States: N. p., 2015. Web. doi:10.1063/1.4905415.
Young, Chadwin D., E-mail: chadwin.young@utdallas.edu, Wang, Zhe, Neugroschel, Arnost, Majumdar, Kausik, Matthews, Ken, & Hobbs, Chris. Investigation of negative bias temperature instability dependence on fin width of silicon-on-insulator-fin-based field effect transistors. United States. doi:10.1063/1.4905415.
Young, Chadwin D., E-mail: chadwin.young@utdallas.edu, Wang, Zhe, Neugroschel, Arnost, Majumdar, Kausik, Matthews, Ken, and Hobbs, Chris. Wed . "Investigation of negative bias temperature instability dependence on fin width of silicon-on-insulator-fin-based field effect transistors". United States. doi:10.1063/1.4905415.
@article{osti_22412963,
title = {Investigation of negative bias temperature instability dependence on fin width of silicon-on-insulator-fin-based field effect transistors},
author = {Young, Chadwin D., E-mail: chadwin.young@utdallas.edu and Wang, Zhe and Neugroschel, Arnost and Majumdar, Kausik and Matthews, Ken and Hobbs, Chris},
abstractNote = {The fin width dependence of negative bias temperature instability (NBTI) of double-gate, fin-based p-type Field Effect Transistors (FinFETs) fabricated on silicon-on-insulator (SOI) wafers was investigated. The NBTI degradation increased as the fin width narrowed. To investigate this phenomenon, simulations of pre-stress conditions were employed to determine any differences in gate oxide field, fin band bending, and electric field profile as a function of the fin width. The simulation results were similar at a given gate stress bias, regardless of the fin width, although the threshold voltage was found to increase with decreasing fin width. Thus, the NBTI fin width dependence could not be explained from the pre-stress conditions. Different physics-based degradation models were evaluated using specific fin-based device structures with different biasing schemes to ascertain an appropriate model that best explains the measured NBTI dependence. A plausible cause is an accumulation of electrons that tunnel from the gate during stress into the floating SOI fin body. As the fin narrows, the sidewall device channel moves in closer proximity to the stored electrons, thereby inducing more band bending at the fin/dielectric interface, resulting in a higher electric field and hole concentration in this region during stress, which leads to more degradation. The data obtained in this work provide direct experimental proof of the effect of electron accumulation on the threshold voltage stability in FinFETs.},
doi = {10.1063/1.4905415},
journal = {Journal of Applied Physics},
number = 3,
volume = 117,
place = {United States},
year = {Wed Jan 21 00:00:00 EST 2015},
month = {Wed Jan 21 00:00:00 EST 2015}
}
  • We report high temperature electrical transport characteristics of a flexible version of the semiconductor industry's most advanced architecture: fin field-effect transistor on silicon-on-insulator with sub-20 nm fins and high-κ/metal gate stacks. Characterization from room to high temperature (150 °C) was completed to determine temperature dependence of drain current (I{sub ds}), gate leakage current (I{sub gs}), transconductance (g{sub m}), and extracted low-field mobility (μ{sub 0}). Mobility degradation with temperature is mainly caused by phonon scattering. The other device characteristics show insignificant difference at high temperature which proves the suitability of inorganic flexible electronics with advanced device architecture.
  • The interface trap generation ({delta}N{sub it}) and fixed oxide charge buildup ({delta}N{sub ot}) under negative bias temperature instability (NBTI) of p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with ultrathin (2 nm) plasma-nitrided SiON gate dielectrics were studied using a modified direct-current-current-voltage method and a conventional subthreshold characteristic measurement. Different stress time dependences were shown for {delta}N{sub it} and {delta}N{sub ot}. At the earlier stress times, {delta}N{sub it} dominates the threshold voltage shift ({delta}V{sub th}) and {delta}N{sub ot} is negligible. With increasing stress time, the rate of increase of {delta}N{sub it} decreases continuously, showing a saturating trend for longer stress times, while {delta}N{submore » ot} still has a power-law dependence on stress time so that the relative contribution of {delta}N{sub ot} increases. The thermal activation energy of {delta}N{sub it} and the NBTI lifetime of pMOSFETs, compared at a given stress voltage, are independent of the peak nitrogen concentration of the SiON film. This indicates that plasma nitridation is a more reliable method for incorporating nitrogen in the gate oxide.« less
  • We use hybrid-functional density functional theory-based Charge Transition Levels (CTLs) to study the electrical activity of near-interfacial oxygen vacancies located in the oxide side of 4H-Silicon Carbide (4H-SiC) power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). Based on the “amorphousness” of their local atomic environment, oxygen vacancies are shown to introduce their CTLs either within (permanently electrically active) or outside of (electrically inactive) the 4H-SiC bandgap. The “permanently electrically active” centers are likely to cause threshold voltage (V{sub th}) instability at room temperature. On the other hand, we show that the “electrically inactive” defects could be transformed into various “electrically active” configurations undermore » simultaneous application of negative bias and high temperature stresses. Based on this observation, we present a model for plausible oxygen vacancy defects that could be responsible for the recently observed excessive worsening of V{sub th} instability in 4H-SiC power MOSFETs under high temperature-and-gate bias stress. This model could also explain the recent electrically detected magnetic resonance observations in 4H-SiC MOSFETs.« less
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