Remarkable charge-trapping efficiency of the memory device with (TiO{sub 2}){sub 0.8}(Al{sub 2}O{sub 3}){sub 0.1} composite charge-storage dielectric
- National Laboratory of Solid State Microstructures, and Department of Materials Science and Engineering, Nanjing University, Nanjing 210093 (China)
- National Laboratory of Solid State Microstructures, and Department of Physics, Nanjing University, Nanjing 210093 (China)
A memory device p-Si/SiO{sub 2}/(TiO{sub 2}){sub 0.8}(Al{sub 2}O{sub 3}){sub 0.1}(TAO-81)/Al{sub 2}O{sub 3}/Pt was fabricated, in which a composite of two high-k dielectrics with a thickness of 1 nm was employed as the charge-trapping layer to enhance the charge-trapping efficiency of the memory device. At an applied gate voltage of ±9 V, TAO-81 memory device shows a memory window of 8.83 V in its C-V curve. It also shows a fast response to a short voltage pulse of 10{sup −5} s. The charge-trapping capability, the endurance, and retention characteristics of TAO-81 memory device can be improved by introducing double TAO-81 charge-trapping layers intercalated by an Al{sub 2}O{sub 3} layer. The charge-trapping mechanism in the memory device is mainly ascribed to the generation of the electron-occupied defect level in the band gap of Al{sub 2}O{sub 3} induced by the inter-diffusion between TiO{sub 2} and Al{sub 2}O{sub 3}.
- OSTI ID:
- 22303912
- Journal Information:
- Applied Physics Letters, Vol. 104, Issue 26; Other Information: (c) 2014 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA); ISSN 0003-6951
- Country of Publication:
- United States
- Language:
- English
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