Electrical characterisation and predictive simulation of defects induced by keV Si{sup +} implantation in n-type Si
- CNRS, LAAS, 7 avenue du colonel Roche, F-31400 Toulouse (France)
- IHP, Im Technologiepark 25, 15236 Frankfurt (Oder) (Germany)
In this work, we focused on the analysis of implantation-induced defects, mainly small interstitial clusters (ICs) and {l_brace} 311{r_brace} defects introduced in n-type Si after ion implantation using deep level transient spectroscopy (DLTS). Silicon ions (at 160 keV or 190 keV) of fluences ranging from (0.1-8.0) Multiplication-Sign 10{sup 13} cm{sup -2} have been implanted into n-type Si and annealed at temperatures between 500 Degree-Sign C and 800 Degree-Sign C specifically to create small ICs or {l_brace} 311{r_brace} s rod-like defects. In samples dominated by small ICs, DLTS spectra show prominent deep levels at Ec - 0.24 eV and Ec - 0.54 eV. After increasing the fluence and temperature, i.e., reducing the number of small ICs and forming {l_brace} 311{r_brace} defects, the peak Ec - 0.54 eV is still dominant while other electron traps Ec - 0.26 eV and Ec - 0.46 eV are introduced. There were no observable deep levels in reference, non-implanted samples. The identity and origin of all these traps are interpreted in conjunction with recently developed predictive defect simulation models.
- OSTI ID:
- 22162912
- Journal Information:
- Journal of Applied Physics, Journal Name: Journal of Applied Physics Journal Issue: 18 Vol. 113; ISSN JAPIAU; ISSN 0021-8979
- Country of Publication:
- United States
- Language:
- English
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