L-connect routing of die surface pads to the die edge for stacking in a 3D array

Patent · Tue Mar 07 00:00:00 EST 2000

OSTI ID:20015695

Petersen, R W

Integrated circuit chips and method of routing the interface pads from the face of the chip or die to one or more sidewall surfaces of the die are disclosed. The interconnection is routed from the face of the die to one or more edges of the die, then routed over the edge of the die and onto the side surface. A new pad is then formed on the sidewall surface, which allows multiple die or chips to be stacked in a three-dimensional array, while enabling follow-on signal routing from the sidewall pads. The routing of the interconnects and formation of the sidewall pads can be carried out in an L-connect or L-shaped routing configuration, using a metalization process such as laser pantography.

• Sponsoring Organization: USDOE
• DOE Contract Number: W-7405-ENG-48
• OSTI ID: 20015695
• Resource Relation: Other Information: PBD: 7 Mar 2000
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
INTEGRATED CIRCUITS
DESIGN
CONNECTORS
INTERFACES
ROUTING