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L-connect routing of die surface pads to the die edge for stacking in a 3D array

Patent ·
OSTI ID:872896
 [1]
  1. Dublin, CA
+ Show Author Affiliations

Integrated circuit chips and method of routing the interface pads from the face of the chip or die to one or more sidewall surfaces of the die. The interconnection is routed from the face of the die to one or more edges of the die, then routed over the edge of the die and onto the side surface. A new pad is then formed on the sidewall surface, which allows multiple die or chips to be stacked in a three-dimensional array, while enabling follow-on signal routing from the sidewall pads. The routing of the interconnects and formation of the sidewall pads can be carried out in an L-connect or L-shaped routing configuration, using a metalization process such as laser pantography.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA
DOE Contract Number:
W-7405-ENG-48
Assignee:
Regents of University of California (Oakland, CA)
Patent Number(s):
US 6034438
OSTI ID:
872896
Country of Publication:
United States
Language:
English

References (3)

The 3D stack in short form (memory chip packaging)
  • Minahan, J. A.; Pepe, A.; Some, R.
  • 1992 42nd Electronic Components & Technology Conference, 1992 Proceedings 42nd Electronic Components & Technology Conference https://doi.org/10.1109/ECTC.1992.204230
conference January 1992
Evaluation of a three-dimensional memory cube system
  • Bertin, C. L.; Perlman, D. J.; Shanken, S. N.
  • IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 16, Issue 8 https://doi.org/10.1109/33.273703
journal January 1993
Area array solder interconnection technology for the three-dimensional silicon cube conference January 1995

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Related Subjects

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