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GPU cache management based on locality type detection

Patent ·
OSTI ID:1986767
Wavefront loading in a processor is managed and includes monitoring a selected wavefront of a set of wavefronts. Reuse of memory access requests for the selected wavefront is counted. A cache hit rate in one or more caches of the processor is determined based on the counted reuse. Based on the cache hit rate, subsequent memory requests of other wavefronts of the set of wavefronts are modified by including a type of reuse of cache lines in requests to the caches. In the caches, storage of data in the caches is based on the type of reuse indicated by the subsequent memory access requests. Reused cache lines are protected by preventing cache line contents from being replaced by another cache line for a duration of processing the set of wavefronts. Caches are bypassed when streaming access requests are made.
Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Santa Clara, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
11,487,671
Application Number:
16/446,119
OSTI ID:
1986767
Country of Publication:
United States
Language:
English

References (6)

Adaptive GPU cache bypassing conference February 2015
Space/time trade-offs in hash coding with allowable errors journal July 1970
Adaptive Cache Management for Energy-Efficient GPU Computing conference December 2014
Access Pattern-Aware Cache Management for Improving Data Utilization in GPU conference June 2017
Priority-based cache allocation in throughput processors conference February 2015
An efficient compiler framework for cache bypassing on GPUs conference November 2013

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