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Title: Dynamic cache bypassing

Patent ·
OSTI ID:1637804
;

A processing system fills a memory access request for data from a processor core by bypassing a cache when a write congestion condition is detected, and when transferring the data to the cache would cause eviction of a dirty cache line. The cache is bypassed by transferring the requested data to the processor core or to a different cache. Accordingly, the processing system can temporarily bypass the cache storing the dirty cache line when filling a memory access request, thereby avoiding the eviction and write back to main memory of a dirty cache line when a write congestion condition exists.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
10,599,578
Application Number:
15/377,537
OSTI ID:
1637804
Resource Relation:
Patent File Date: 12/13/2016
Country of Publication:
United States
Language:
English

References (10)

Selective Storage of Data in Levels of a Cache Memory patent-application March 2008
Cache and Method for Cache Bypass Functionality patent-application May 2008
Open high speed bus for microcomputer system patent May 1996
Cache Lookup Bypass in Multi-Level Cache Systems patent-application November 2015
Data storage apparatus and methods patent December 2014
State Encoding for Cache Lens patent-application June 2014
Speculative cache line write backs to avoid hotspots patent September 2000
Cache Memory Bypass in a Multi-Core Processor (MCP) patent-application May 2010
Data Bus Efficiency via Cache Line Usurpation patent-application July 2009
Reducing cache misses by snarfing writebacks in non-inclusive memory systems patent June 1999

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97 MATHEMATICS AND COMPUTING