Dynamic cache bypassing
Patent
·
OSTI ID:1637804
A processing system fills a memory access request for data from a processor core by bypassing a cache when a write congestion condition is detected, and when transferring the data to the cache would cause eviction of a dirty cache line. The cache is bypassed by transferring the requested data to the processor core or to a different cache. Accordingly, the processing system can temporarily bypass the cache storing the dirty cache line when filling a memory access request, thereby avoiding the eviction and write back to main memory of a dirty cache line when a write congestion condition exists.
- Research Organization:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC52-07NA27344
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- Patent Number(s):
- 10,599,578
- Application Number:
- 15/377,537
- OSTI ID:
- 1637804
- Country of Publication:
- United States
- Language:
- English
Similar Records
GPU cache management based on locality type detection
Device and method for cache utilization aware data compression
Preemptive cache management policies for processing units
Patent
·
Tue Nov 01 00:00:00 EDT 2022
·
OSTI ID:1986767
Device and method for cache utilization aware data compression
Patent
·
Mon Nov 16 23:00:00 EST 2020
·
OSTI ID:1771643
Preemptive cache management policies for processing units
Patent
·
Tue May 28 00:00:00 EDT 2019
·
OSTI ID:1568401