Latency hiding for caches

Kalamatianos, John; Kokolis, Apostolos; Ganapathy, Shrikanth

Latency hiding for caches

Patent · Tue Jul 26 04:00:00 EDT 2022

OSTI ID:1924927

Kalamatianos, John; Kokolis, Apostolos; Ganapathy, Shrikanth

A technique for accessing a memory having a high latency portion and a low latency portion is provided. The technique includes detecting a promotion trigger to promote data from the high latency portion to the low latency portion, in response to the promotion trigger, copying cache lines associated with the promotion trigger from the high latency portion to the low latency portion, and in response to a read request, providing data from either or both of the high latency portion or the low latency portion, based on a state associated with data in the high latency portion and the low latency portion.

Research Organization:: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Organization:: USDOE

DOE Contract Number:: AC52-07NA27344

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Number(s):: 11,397,691

Application Number:: 16/683,142

OSTI ID:: 1924927

Country of Publication:: United States

Language:: English

References (10)

Adaptive placement and migration policy for an STT-RAM-based hybrid cache Wang, Zhe; Jimenez, Daniel A.; Xu, Cong 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) https://doi.org/10.1109/HPCA.2014.6835933	conference	February 2014
Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache Korgaonkar, Kunal; Bhati, Ishwar; Liu, Huichu 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA) https://doi.org/10.1109/ISCA.2018.00035	conference	June 2018
Evaluating STT-RAM as an energy-efficient main memory alternative Kultursay, Emre; Kandemir, Mahmut; Sivasubramaniam, Anand 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) https://doi.org/10.1109/ISPASS.2013.6557176	conference	April 2013
Prefetching techniques for STT-RAM based last-level cache in CMP systems Mao, Mengjie; Sun, Guangyu; Li, Yong 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) https://doi.org/10.1109/ASPDAC.2014.6742868	conference	January 2014
Performance and Energy-Efficient Design of STT-RAM Last-Level Cache Hameed, Fazal; Khan, Asif Ali; Castrillon, Jeronimo IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, Issue 6 https://doi.org/10.1109/TVLSI.2018.2804938	journal	June 2018
OAP: An Obstruction-Aware Cache Management Policy for STT-RAM Last-Level Caches Wang, Jue; Dong, Xiangyu; Xie, Yuan Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 https://doi.org/10.7873/DATE.2013.179	conference	January 2013
Spatial Locality-Aware Cache Partitioning for Effective Cache Sharing Gupta, Saurabh; Zhou, Huiyang 2015 44th International Conference on Parallel Processing https://doi.org/10.1109/ICPP.2015.24	conference	September 2015
Read Performance: The Newest Barrier in Scaled STT-RAM Zhang, Yaojun; Li, Yong; Sun, Zhenyu IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, Issue 6 https://doi.org/10.1109/TVLSI.2014.2326797	journal	June 2015
Multi retention level STT-RAM cache designs with a dynamic refresh scheme Sun, Zhenyu; Bi, Xiuyuan; Li, Hai (Helen) Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture https://doi.org/10.1145/2155620.2155659	conference	December 2011
Relaxing non-volatility for fast and energy-efficient STT-RAM caches Smullen, Clinton W.; Mohan, Vidyabhushan; Nigam, Anurag 2011 IEEE 17th International Symposium on High Performance Computer Architecture https://doi.org/10.1109/HPCA.2011.5749716	conference	February 2011

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