Selective data retrieval based on access latency

Patent · Tue Dec 10 04:00:00 EST 2019

OSTI ID:1600387

Eckert, Yasuko

A processor includes multiple processing units (e.g., processor cores), with each processing unit associated with at least one private, dedicated cache. The processor is also associated with a system memory that stores all data that can be accessed by the multiple processing units. A coherency manager (e.g., a coherence directory) of the processor enforces a specified coherency scheme to ensure data coherency between the different caches and between the caches and the system memory. In response to a memory access request to a given cache resulting in a cache miss, the coherency manager identifies the current access latency to the system memory as well as the current access latencies to other caches of the processor. The coherency manager transfers the targeted data to the given cache from the cache or system memory having the lower access latency.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC52-07NA27344
• Assignee: Advanced Micro Devices, Inc. (Santa Clara, CA)
• Patent Number(s): 10,503,640
• Application Number: 15/960,875
• OSTI ID: 1600387
• Country of Publication: United States
• Language: English

Related Subjects

97 MATHEMATICS AND COMPUTING