An empirical evaluation of the convex SPP-1000 hierarchical shared memory system

Journal Article · Thu Aug 01 04:00:00 EDT 1996 · International Journal of Parallel Programming

OSTI ID:441129

Sterling, T; Olson, K

Cache coherency in a scalable parallel computer architecture requires mechanisms beyond the conventional common bus based snooping approaches which are limited to about 16 processors. The new Convex SPP-1000 achieves cache coherency across 128 processors through a two-level shared memory NUMA structure employing directory based and SCI protocol mechanisms. While hardware support for managing a common global name space minimizes overhead costs and simplifies programming, latency considerations for remote accesses may still dominate and can under unfavorable conditions constrain scalability. This paper provides the first published evaluation of the SP-1000 hierarchical cache coherency mechanisms from the perspective of measured latency and its impact on basic global flow control mechanisms, scaling of a parallel science code, and sensitivity of cache miss rates to system scale. It is shown that global remote access latency is only a factor of seven greater than that of local cache miss penalty and that scaling of a challenging scientific application is not severely degraded by the hierarchical structure for achieving consistency across the system processor caches.

• OSTI ID: 441129
• Journal Information: International Journal of Parallel Programming, Journal Name: International Journal of Parallel Programming Journal Issue: 4 Vol. 24; ISSN IJPPE5; ISSN 0885-7458
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
ARRAY PROCESSORS
MEMORY DEVICES
PARALLEL PROCESSING
PERFORMANCE TESTING