DynPaC: Coarse-Grained, Dynamic, and Partially Reconfigurable Array for Streaming Applications

Conference · Mon Dec 20 04:00:00 EST 2021

DOI:https://doi.org/10.1109/ICCD53106.2021.00018· OSTI ID:1855425

Tan, Cheng ^[1]; Geng, Tong ^[1]; Xie, Chenhao ^[1]; Bohm Agostini, Nicolas ^[1]; Li, Jiajia ^[1]; Li, Ang ^[1]; Barker, Kevin J. ^[1]; Tumeo, Antonino ^[1]

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1. BATTELLE (PACIFIC NW LAB)

Coarse-grained reconfigurable arrays (CGRAs) provide higher flexibility than application-specific integrated circuits (ASICs) and higher efficiency than fine-grained reconfigurable devices such as Field Programmable Gate Arrays (FPGAs). However, CGRAs are generally designed to support offloading of a single kernel. While their design, based on communicating functional units, appears to naturally suit streaming applications composed of multiple cooperating kernels, current approaches only statically partition the resources across kernels. However, streaming applications often are data-dependent, leading to variable kernel execution times depending on the input data and impacting the throughput of the entire pipeline if resources are statically allocated. Therefore, in this paper, we discuss the design of DynPaC — a coarse-grained, dynamically, and partially reconfigurable array for data-dependent streaming applications. We discuss the required software and hardware components to manage partial dynamic reconfiguration. We demonstrate that by supporting partial dynamic reconfiguration, we can obtain an average speedup of 1.44X for a representative set of applications w.r.t. static partitioning, with a limited area overhead (6.4% of the entire chip).

• Research Organization: Pacific Northwest National Laboratory (PNNL), Richland, WA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC05-76RL01830
• OSTI ID: 1855425
• Report Number(s): PNNL-SA-163151
• Country of Publication: United States
• Language: English