ICED: An Integrated CGRA Framework Enabling DFVS-Aware Acceleration

Conference · Mon Nov 04 04:00:00 EST 2024

DOI:https://doi.org/10.1109/MICRO61859.2024.00099· OSTI ID:2564121

Tan, Cheng ^[1]; Jiang, Miaomiao ^[2]; Patil, Deepak ^[3]; Ou, Yanghui ^[4]; Li, Zhaoying ^[5]; Ju, Lei ^[2]; Mitra, Tulika ^[5]; Park, Hyunchul ^[1]; Tumeo, Antonino ^[6]; Zhang, Jeff ^[3]

---

1. Google
2. Shandong University
3. Arizona State University
4. Cornell University
5. National University of Singapore
6. BATTELLE (PACIFIC NW LAB)

oarse-grained reconfigurable arrays (CGRAs) are a promising solution to enable energy-efficient acceleration of applications from different domains. By leveraging reconfiguration at the functional level, they can adapt to significantly different computational patterns. Existing CGRA mapping approaches extract instruction-level parallelism, exploit loop-pipelining opportunities, guarantee the data dependency, and target high throughput of a given loop. However, the recurrence data-dependency in the DFG and the mismatch between required and available computing/communication resources complicate the mapping, and might lead to significant unbalances in the utilization of the CGRA's tiles. This results in wasted power for tiles with low utilization. Applying dynamic voltage and frequency scaling (DVFS) can potentially solve this challenge and improve energy efficiency by adjusting voltage and frequency of different tiles independently. CGRAs have also been successful in accelerating data-dependent streaming applications. However, in these applications, the execution time of each kernel in the pipeline might dynamically vary depending on the characteristics of the input. This also leads to under-utilization of resources for the dynamically changing kernels that do not limit the application throughput. DVFS can also improve energy efficiency for these applications by dynamically changing the voltage and frequency levels of tiles that host non performance-constraining kernels. This paper proposes ICEDTEA -- an integrated DVFS-aware framework to map applications on CGRAs that support power islands. ICEDTEA proposes a CGRA architecture supporting DVFS islands at varying granularity (from a single tile to a group of tiles) and the related DVFS-aware compilation and mapping toolchain. ICEDTEA is the first work that introduces DVFS support for spatio-temporal CGRAs at power-island levels. The experimental evaluation shows that ICEDTEA improves average utilization by 2.3$$\times$$ and energy-efficiency by 1.32$$\times$$ over a conventional CGRA. With streaming applications, ICEDTEA improves energy efficiency by 1.12$$\times$$ over a state-of-the-art CGRA that introduces partial dynamic reconfiguration to adapt to variations in kernels' throughput.

• Research Organization: Pacific Northwest National Laboratory (PNNL), Richland, WA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC05-76RL01830
• OSTI ID: 2564121
• Report Number(s): PNNL-SA-193021
• Country of Publication: United States
• Language: English