AURORA: Automated Refinement of Coarse-Grained Reconfigurable Accelerators

Conference · Mon Feb 01 04:00:00 EST 2021

OSTI ID:1820385

Tan, Cheng ^[1]; Xie, Chenhao ^[1]; Li, Ang ^[1]; Barker, Kevin J. ^[1]; Tumeo, Antonino ^[1]

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1. BATTELLE (PACIFIC NW LAB)

Coarse-grained reconfigurable arrays (CGRAs), loosely defined as arrays of functional units interconnected through a network-on-chip (NoC), provide higher flexibility than domain-specific ASIC accelerators while offering increased hardware efficiency with respect to fine-grained reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs). Un-fortunately, designing a CGRA for a specific application domain involves enormous software/hardware engineering effort (e.g., designing the CGRA, map operations onto the CGRA, etc) and requires the exploration on a large design space (e.g., applying appropriate loop transformation on each application, specializing the reconfigurable processing elements of the CGRA, refining the network topology, deciding the size of the data memory, etc). Int his paper, we propose AURORA – a software/hardware co-design framework to automatically synthesize optimal CGRA given a set of applications of interest

• Research Organization: Pacific Northwest National Laboratory (PNNL), Richland, WA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC05-76RL01830
• OSTI ID: 1820385
• Report Number(s): PNNL-SA-156552
• Country of Publication: United States
• Language: English