Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sandia National Lab. (SNL-CA), Livermore, CA (United States)
- Los Alamos National Lab. (LANL), Los Alamos, NM (United States)
- Arizona State Univ., Tempe, AZ (United States)
Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor’s scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Furthermore, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop’s sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.
- Research Organization:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Sandia National Lab. (SNL-CA), Livermore, CA (United States)
- Sponsoring Organization:
- USDOE National Nuclear Security Administration (NNSA)
- Grant/Contract Number:
- AC04-94AL85000
- OSTI ID:
- 1787522
- Report Number(s):
- SAND-2021-4082J; 695305
- Journal Information:
- IEEE Transactions on Nuclear Science, Vol. 68, Issue 5; ISSN 0018-9499
- Publisher:
- IEEECopyright Statement
- Country of Publication:
- United States
- Language:
- English
Similar Records
Soft error-mitigating semiconductor design system and associated methods
LADR: low-cost application-level detector for reducing silent output corruptions