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Method and apparatus for maintaining data coherence in a non-uniform compute device

Patent ·
OSTI ID:1771480
; ;
A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. Data coherence is maintained by control logic that blocks access to data locations in use by a selected processing unit other than the selected processing unit until data associated with the data locations are released from the reorder buffer. Data stored in the cache is written to the memory if it is already in a modified state, otherwise the state is set to the modified state. A memory controller may be used to restrict access to memory locations to be operated on.
Research Organization:
ARM Ltd., Cambridge (United Kingdom)
Sponsoring Organization:
USDOE
Assignee:
Arm Limited (Cambridge, GB)
Patent Number(s):
10,795,815
Application Number:
15/166,458
OSTI ID:
1771480
Country of Publication:
United States
Language:
English

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Related Subjects

97 MATHEMATICS AND COMPUTING