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Method and apparatus for reordering in a non-uniform compute device

Patent ·
OSTI ID:1600162
; ;
A data processing apparatus includes a multi-level memory system, one or more first processing unit coupled to the memory system at a first level and one or more second processing units each coupled to the memory system at a second level. A first reorder buffer maintains data order during execution of instructions by the first and second processing units and a second reorder buffer maintains data order during execution of the instructions by an associated second processing unit. An entry in the first reorder buffer is configured, dependent upon an indicator bit, as an entry for a single instruction or a pointer to an entry in the second reorder buffer. An entry in the second reorder buffer includes instruction block start and end addresses and indicators of input and output register. Instructions are released to a processing unit when all inputs, as indicated by the reorder buffers, are available.
Research Organization:
ARM Limited, Cambridge (United Kingdom)
Sponsoring Organization:
USDOE
Assignee:
ARM Limited (Cambridge, GB)
Patent Number(s):
10,445,094
Application Number:
15/166,467
OSTI ID:
1600162
Country of Publication:
United States
Language:
English

References (10)

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conference January 2013
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conference June 2015
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs
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conference October 2016
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Related Subjects

97 MATHEMATICS AND COMPUTING