A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS) specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS), bipolar (Bi) and BiCMOS chips applications, is presented in this review article.
Pavunny, Shojan, et al. "Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices." Materials, vol. 7, no. 4, Mar. 2014. https://doi.org/10.3390/ma7042669
Pavunny, Shojan, Scott, James, & Katiyar, Ram (2014). Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices. Materials, 7(4). https://doi.org/10.3390/ma7042669
Pavunny, Shojan, Scott, James, and Katiyar, Ram, "Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices," Materials 7, no. 4 (2014), https://doi.org/10.3390/ma7042669
@article{osti_1628445,
author = {Pavunny, Shojan and Scott, James and Katiyar, Ram},
title = {Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices},
annote = {A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS) specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS), bipolar (Bi) and BiCMOS chips applications, is presented in this review article.},
doi = {10.3390/ma7042669},
url = {https://www.osti.gov/biblio/1628445},
journal = {Materials},
issn = {ISSN MATEG9},
number = {4},
volume = {7},
place = {United States},
publisher = {MDPI},
year = {2014},
month = {03}}
12th International Pulsed Power Conference, Digest of Technical Papers. 12th IEEE International Pulsed Power Conference. (Cat. No.99CH36358)https://doi.org/10.1109/ppc.1999.825422
Conference
·
Sat Aug 01 00:00:00 EDT 1992
· IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States)
·OSTI ID:7065689