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Title: Virtual FPGA management and optimization system

Patent ·
OSTI ID:1531398
; ;

A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344; B620717
Assignee:
Advanced Micro Devices, Inc. (Sunnyvale, CA)
Patent Number(s):
10,164,639
Application Number:
15/812,411
OSTI ID:
1531398
Resource Relation:
Patent File Date: 2017-11-14
Country of Publication:
United States
Language:
English

References (19)

3D integrated circuits using thick metal for backside connections and offset bumps patent August 2008
Compression and decompression of configuration data using repeated data frames patent March 2011
Die-Stacked Memory Device with Reconfigurable Logic patent-application June 2015
Architecture of field-programmable gate arrays journal July 1993
Network interface unit including a microcontroller having multiple configurable logic blocks, with a test/program bus for performing a plurality of selected functions patent May 2001
Reprogrammable instruction set accelerator patent April 1998
Methods and systems for assigning non-continual jobs to candidate processing nodes in a stream-oriented computer system patent June 2013
Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux conference March 2007
Method and apparatus for controlling a processor in a data processing system patent July 2007
Virtualized Execution Runtime for FPGA Accelerators in the Cloud journal January 2017
Hierarchical Staging Areas for Scheduling Threads for Execution patent-application April 2015
Run-time support for heterogeneous multitasking on reconfigurable SoCs journal October 2004
An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems
  • Santambrogio, M. D.; Cancare, F.; Cattaneo, R.
  • 2012 26th IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum https://doi.org/10.1109/IPDPSW.2012.41
conference May 2012
Emulating power domains in an integrated circuit using partial reconfiguration patent January 2015
FPGA and CPLD architectures: a tutorial journal July 1996
Controlling Fair Bandwidth Allocation Efficiently patent-application July 2016
Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM patent July 2000
A VLIW processor with reconfigurable instruction set for embedded applications journal November 2003
Redundancy structures and methods in a programmable logic device patent February 2007

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