Virtual FPGA management and optimization system
Abstract
A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.
- Inventors:
- Publication Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1531398
- Patent Number(s):
- 10,164,639
- Application Number:
- 15/812,411
- Assignee:
- Advanced Micro Devices, Inc. (Sunnyvale, CA)
- DOE Contract Number:
- AC52-07NA27344; B620717
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2017-11-14
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Roberts, David A., Kegel, Andrew G., and Mednick, Elliot H. Virtual FPGA management and optimization system. United States: N. p., 2018.
Web.
Roberts, David A., Kegel, Andrew G., & Mednick, Elliot H. Virtual FPGA management and optimization system. United States.
Roberts, David A., Kegel, Andrew G., and Mednick, Elliot H. 2018.
"Virtual FPGA management and optimization system". United States. https://www.osti.gov/servlets/purl/1531398.
@article{osti_1531398,
title = {Virtual FPGA management and optimization system},
author = {Roberts, David A. and Kegel, Andrew G. and Mednick, Elliot H.},
abstractNote = {A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.},
doi = {},
url = {https://www.osti.gov/biblio/1531398},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Dec 25 00:00:00 EST 2018},
month = {Tue Dec 25 00:00:00 EST 2018}
}
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