Skip to main content
U.S. Department of Energy
Office of Scientific and Technical Information

Extending the constrained random simulation methodology into physical device verification for Processor-based ASICs.

Conference ·
OSTI ID:1422153

Abstract not provided.

Research Organization:
Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
Sponsoring Organization:
USDOE National Nuclear Security Administration (NNSA).
DOE Contract Number:
AC04-94AL85000
OSTI ID:
1422153
Report Number(s):
SAND2016-0687C; 643544
Country of Publication:
United States
Language:
English

Similar Records

Extending the Constrained Random Simulation Methodology into Physical Device Verification of an Embedded Processor ASIC.
Conference · Mon Feb 29 23:00:00 EST 2016 · OSTI ID:1346117

Formal Verification of Digital ASICs.
Conference · Mon Feb 29 23:00:00 EST 2016 · OSTI ID:1346887

Semi-Supervised Learning and ASIC Path Verification.
Conference · Sun Apr 01 00:00:00 EDT 2018 · OSTI ID:1506578

Related Subjects