Low-noise CMOS signal processing IC for interpolating cathode strip chambers
- Brookhaven National Lab., Upton, NY (United States)
A CMOS circuit for obtaining precision amplitude and timing information from the cathodes of a proportional chamber with interpolating cathode strips has been developed. The chip performs charge amplification, shaping, analog storage and multiplexing, and generates a prompt timing pulse which can be used for trigger purposes. Novel features of the IC include: preamplifier optimized for large (40--250pF) detector capacitance, digitally programmable gain and bandwidth of the fourth-order shaper, and an array of on-chip capacitors and switches for injecting charge for calibration. Noise is less than 1,500 r.m.s. electrons with an input capacitance of 100 pF using bipolar 550 nsec shaping. Linearity is better than 0.8% over a dynamic range of 1,500:1. The constant fraction discriminator has a time walk of {+-}2.5 nsec over the range 10--500 fC. Power dissipation is 50 mW per channel.
- Research Organization:
- Brookhaven National Laboratory (BNL), Upton, NY
- DOE Contract Number:
- AC02-76CH00016
- OSTI ID:
- 136911
- Report Number(s):
- CONF-941061--
- Journal Information:
- IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 4Pt1 Vol. 42; ISSN 0018-9499; ISSN IETNAE
- Country of Publication:
- United States
- Language:
- English
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