Cryogenic Lifetime Studies of 130 nm and 65 nm CMOS Technologies for High-Energy Physics Experiments
Journal Article
·
· IEEE Transactions on Nuclear Science
- Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
- Southern Methodist Univ., Dallas, TX (United States)
The Long Baseline Neutrino Facility intends to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. Research is under way to place the electronics inside the cryostat. For reasons of efficiency and economics, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This, then, requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130 nm and 65 nm nMOS transistors operating at cryogenic temperatures are investigated. Our results show that both technologies achieve the lifetimes required by the experiment. Minimal design changes are necessary in the case of the 130 nm process and no changes whatsoever are necessary for the 65 nm process.
- Research Organization:
- Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25)
- DOE Contract Number:
- AC02-07CH11359
- OSTI ID:
- 1230026
- Report Number(s):
- FERMILAB-PUB--15-078-PPD
- Journal Information:
- IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 3 Vol. 62; ISSN 0018-9499
- Publisher:
- Institute of Electrical and Electronics Engineers (IEEE)
- Country of Publication:
- United States
- Language:
- English
Similar Records
Lifetime studies of 130nm nMOS transistors intended for long-duration, cryogenic high-energy physics experiments.
Scaling trends in SET pulse widths in Sub-100 nm bulk CMOS processes.
Monolithic Integration of Lateral HV Power MOSFET with LV CMOS for SiC Power IC Technology
Conference
·
Wed Nov 30 23:00:00 EST 2011
· Submitted to IEEE Trans.Nucl.Sci.
·
OSTI ID:1032886
Scaling trends in SET pulse widths in Sub-100 nm bulk CMOS processes.
Conference
·
Thu Jul 01 00:00:00 EDT 2010
·
OSTI ID:1021643
Monolithic Integration of Lateral HV Power MOSFET with LV CMOS for SiC Power IC Technology
Conference
·
Sun May 30 00:00:00 EDT 2021
· 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD)
·
OSTI ID:1825459