Dual-Edge Signaling Logic

Technical Report · Wed Apr 01 04:00:00 EDT 2015

DOI:https://doi.org/10.2172/1178950· OSTI ID:1178950

Resnick, David Richard ^[1]

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1. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

The single-pulse nature of Josephson junction (JJ) logic functions makes logic design harder to do and not at all familiar to pretty much all people who might want to design using JJs—in effect, logic zeros are missing and the logic must be somewhat more complex in implementation to ‘get around’ that. One result of the single-sided logic is that a constant clock function is needed for most all the individual logic functions and gates in current JJ design styles to work. The resultant clock distribution is thus large and takes a large proportion of the logic energy. Here is a proposal for a different kind of logic design style and function that may well overcome most of the difficulties mentioned above. If the logic functionality shown here can actually be brought to life, it would be interesting to assess its impact in area, in energy usage, ease of design, etc.

• Research Organization: Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
• Sponsoring Organization: USDOE Office of Science (SC), Advanced Scientific Computing Research (ASCR) (SC-21)
• DOE Contract Number: AC04-94AL85000
• OSTI ID: 1178950
• Report Number(s): SAND--2015-3286R; 583485
• Country of Publication: United States
• Language: English

Related Subjects

97 MATHEMATICS AND COMPUTING