Method and system for selecting data sampling phase for self timed interface logic
Patent
·
OSTI ID:1175195
An exemplary embodiment of the present invention is a method for transmitting data among processors over a plurality of parallel data lines and a clock signal line. A receiver processor receives both data and a clock signal from a sender processor. At the receiver processor a bit of the data is phased aligned with the transmitted clock signal. The phase aligning includes selecting a data phase from a plurality of data phases in a delay chain and then adjusting the selected data phase to compensate for a round-off error. Additional embodiments include a system and storage medium for transmitting data among processors over a plurality of parallel data lines and a clock signal line.
- Research Organization:
- International Business Machines Corporation, Armonk, NY (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- W-7405-ENG-48
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Number(s):
- 6,839,861
- Application Number:
- 09/918,081
- OSTI ID:
- 1175195
- Country of Publication:
- United States
- Language:
- English
Similar Records
Interprocessor communication
Multi-channel time-reversal receivers for multi and 1-bit implementations
Hardware multiplier processor
Patent
·
1989
·
OSTI ID:6215336
Multi-channel time-reversal receivers for multi and 1-bit implementations
Patent
·
2008
·
OSTI ID:958719
Hardware multiplier processor
Patent
·
1985
·
OSTI ID:865855