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Design of digital circuits using inverse-mode cascode SiGe HBTs for single event upset mitigation.

Conference ·
OSTI ID:1021641
 [1];  [1]; ;  [1];  [2]; ;  [3];  [1]
  1. Georgia Institute of Technology, Atlanta, GA
  2. Consultant to NASA, Brookneal, VA
  3. NASA Goddard Space Flight Center, Greenbelt, MD

We report on the design and measured results of a new SiGe HBT radiation hardening by design technique called the 'inverse-mode cascode' (IMC). A third-generation SiGe HBT IMC device was tested in a time resolved ion beam induced charge collection (TRIBICC) system, and was found to have over a 75% reduction in peak current transients with the use of an n-Tiedown on the IMC sub-collector node. Digital shift registers in a 1st-generation SiGe HBT technology were designed and measured under a heavy-ion beam, and shown to increase the LET threshold over standard npn only shift registers. Using the CREME96 tool, the expected orbital bit-errors/day were simulated to be approximately 70% lower with the IMC shift register. These measured results help demonstrate the efficacy of using the IMC device as a low-cost means for improving the SEE radiation hardness of SiGe HBT technology without increasing area or power.

Research Organization:
Sandia National Laboratories
Sponsoring Organization:
USDOE
DOE Contract Number:
AC04-94AL85000
OSTI ID:
1021641
Report Number(s):
SAND2010-4815C
Country of Publication:
United States
Language:
English

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