Complementary GaAs junction-gated heterostructure field effect transistor fabrication for integrated circuits
A new GaAs junction-gated complementary logic technology that integrates a modulation doped p-channel heterostructure field effect transistor (pHFET) and a fully ion implanted n-channel JFET has recently been fabricated. High-speed, low-power operation has been demonstrated with loaded ring oscillators that show gate delays of 179 ps/stage for a power-delay product of 28 fJ at 1.2 V operation and 320 ps/stage and 8.9 fJ at 0.8 V operation. The principal advantages of this technology include the ability to independently set the threshold voltage of n- and p-channel devices and to independently design the pHFET for high performance. A self-aligned refractory gate process based on tungsten and tungsten silicide gate metal has been used to fabricate the FETs. Novel aspects of the fabrication include the simultaneous formation of non-alloyed, refractory ohmic contacts for the junction gates and the formation of shallow p-n junctions by ion implantation.
- Research Organization:
- Sandia National Labs., Albuquerque, NM (United States)
- Sponsoring Organization:
- USDOE, Washington, DC (United States)
- DOE Contract Number:
- AC04-94AL85000
- OSTI ID:
- 10189609
- Report Number(s):
- SAND--94-1670C; CONF-941063--7; ON: DE95001522
- Country of Publication:
- United States
- Language:
- English
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