Complementary HFET technology for wireless digital and microwave applications
- and others
Development of a complementary heterostructure field effect transistor (CHFET) technology for low-power, mixed-mode digital-microwave applications is presented. Digital CHFET technology with independently optimizable transistors has been shown to operate with 319 ps loaded gate delays at 8.9 fJ. Power consumption is dominated by leakage currents of the p-channel FET, while performance is determined by the characteristics of 0.7 {mu}m gate length devices. As a microwave technology, the nJFET forms the basis of low-power cirucitry without any modification to the digital process. Narrow band amplification with a 0.7x100 {mu}m nJFET has been demonstrated at 2.1-2.4 GHz with gains of 8-10 dB at 1 mW power. These amplifiers showed a minimum noise figure of 2.5 dB. Next generation CHFET transistors with sub 0.5 {mu}m gate lengths have also been developed. Cutoff frequencies of 49 and 11.5 GHz were achieved for n- and p-channel FETs with 0.3 and 0.4 {mu}m gates, respectively. These FETs will enable enhancements in both digital and microwave circuits.
- Research Organization:
- Sandia National Labs., Albuquerque, NM (United States)
- Sponsoring Organization:
- USDOE, Washington, DC (United States)
- DOE Contract Number:
- AC04-94AL85000
- OSTI ID:
- 378691
- Report Number(s):
- SAND--96-2006C; CONF-961040--4; ON: DE96014839
- Country of Publication:
- United States
- Language:
- English
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