I{sub DDQ} testing for ultimate low power design verification and defect detection

Conference · Fri Jul 01 00:00:00 EDT 1994

OSTI ID:10162907

Hawkins, C F ^[1]; Hewlett, F W; Soden, J M ^[2]

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1. New Mexico Univ., Albuquerque, NM (United States). Dept. of Electrical and Computer Engineering
2. Sandia National Labs., Albuquerque, NM (United States)

I{sub DDQ} testing is mandatory to ensure that low power CMOS ICs meet their design intent. I{sub DDQ} testing is both a design verifier for low quiescent current and a sensitive production test for defects. Quiescent power reduction is particularly important for products such as cardiac pacemakers, laptop computers, and cellular telephones.

• Research Organization: Sandia National Labs., Albuquerque, NM (United States)
• Sponsoring Organization: USDOE, Washington, DC (United States)
• DOE Contract Number: AC04-94AL85000
• OSTI ID: 10162907
• Report Number(s): SAND--94-1316C; CONF-941087--1; ON: DE94014281; BR: GB0103012
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000
COMPONENTS
ELECTRON DEVICES AND CIRCUITS
DEFECTS
ELECTRICAL TESTING
INTEGRATED CIRCUITS
QUALITY CONTROL
SCANNING ELECTRON MICROSCOPY