Reader set encoding for directory of shared cache memory in multiprocessor system

Ahn, Dnaiel; Ceze, Luis H.; Gara, Alan; Ohmacht, Martin; Xiaotong, Zhuang

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Title: Reader set encoding for directory of shared cache memory in multiprocessor system

Abstract

In a parallel processing system with speculative execution, conflict checking occurs in a directory lookup of a cache memory that is shared by all processors. In each case, the same physical memory address will map to the same set of that cache, no matter which processor originated that access. The directory includes a dynamic reader set encoding, indicating what speculative threads have read a particular line. This reader set encoding is used in conflict checking. A bitset encoding is used to specify particular threads that have read the line.

Inventors:: Ahn, Dnaiel; Ceze, Luis H.; Gara, Alan; Ohmacht, Martin; Xiaotong, Zhuang

Issue Date:: Tue Jun 10 00:00:00 EDT 2014

Research Org.:: International Business Machines Corporation, Armonk, NY (USA)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1134016

Patent Number(s):: 8751748

Application Number:: 13/008,583

Assignee:: International Business Machines Corporation

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/08 - in hierarchically structured memory systems, e.g. virtual memory systems
G06F12/084 - with a shared cache
G06F12/0842 - for multiprocessing or multitasking
G06F9/524 - {Deadlock detection or avoidance}

Show less

DOE Contract Number:: B554331

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Ahn, Dnaiel, Ceze, Luis H., Gara, Alan, Ohmacht, Martin, and Xiaotong, Zhuang. Reader set encoding for directory of shared cache memory in multiprocessor system.  United States: N. p., 2014. 
        Web.

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                    Ahn, Dnaiel, Ceze, Luis H., Gara, Alan, Ohmacht, Martin, & Xiaotong, Zhuang. Reader set encoding for directory of shared cache memory in multiprocessor system.  United States.

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                    Ahn, Dnaiel, Ceze, Luis H., Gara, Alan, Ohmacht, Martin, and Xiaotong, Zhuang. Tue .  
        "Reader set encoding for directory of shared cache memory in multiprocessor system".  United States.  https://www.osti.gov/servlets/purl/1134016.

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@article{osti_1134016,

  title        = {Reader set encoding for directory of shared cache memory in multiprocessor system},

  author       = {Ahn, Dnaiel and Ceze, Luis H. and Gara, Alan and Ohmacht, Martin and Xiaotong, Zhuang},

  abstractNote = {In a parallel processing system with speculative execution, conflict checking occurs in a directory lookup of a cache memory that is shared by all processors. In each case, the same physical memory address will map to the same set of that cache, no matter which processor originated that access. The directory includes a dynamic reader set encoding, indicating what speculative threads have read a particular line. This reader set encoding is used in conflict checking. A bitset encoding is used to specify particular threads that have read the line.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Tue Jun 10 00:00:00 EDT 2014},

  month        = {Tue Jun 10 00:00:00 EDT 2014}

}

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Works referencing / citing this record:

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Title: Reader set encoding for directory of shared cache memory in multiprocessor system

Abstract

Citation Formats

Processor associated blocking symbol controls for serializing the accessing of data resources in a computer system patent, April 1999

Eviction override for larx-reserved addresses patent, April 2001

Apparatus and method for preventing cache data eviction during an atomic operation patent, February 2002

System and method providing cache coherency and atomic memory operations in a multiprocessor computer architecture patent, March 2002

Detecting full conditions in a queue patent, October 2002

Multi-thread packet processor patent-application, June 2002

Cache way prediction based on instruction base register patent-application, September 2002

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Stall technique to facilitate atomicity in processor execution of helper set patent-application, September 2004

Synchronization of parallel processes patent-application, September 2005

Processor with cache way prediction and method thereof patent-application, May 2006

Implementation of load linked and store conditional operations patent-application, July 2006

Apparatus and method for sparse line write transactions patent-application, February 2007

Separate data/coherency caches in a shared memory multiprocessor system patent-application, July 2007

Architectural support for thread level speculative execution patent-application, August 2007

Snoop Filter Directory Mechanism in Coherency Shared Memory System patent-application, December 2007

Prefetch Miss Indicator for Cache Coherence Directory Misses on External Caches patent-application, August 2008

Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory patent-application, December 2008

Method and Apparatus for Employing Multi-Bit Register File Cells and SMT Thread Groups patent-application, December 2008

System and Method for Executing Nested Atomic Blocks Using Split Hardware Transactions patent-application, January 2009

Enabling Speculative State Information in a Cache Coherency Protocol patent-application, March 2009

Efficient Deterministic Multiprocessing patent-application, September 2009

Early header CRC in data response packets with variable gap count patent-application, October 2009

Method, System and Apparatus for Reducing Memory Traffic in a Distributed Memory System patent-application, November 2009

Cache control device and control method patent-application, July 2010

Using Time Stamps to Facilitate Load Reordering patent-application, August 2010

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Bulk Disambiguation of Speculative Threads in Multiprocessors conference, January 2006

Identifying performance limiting internode data sharing on NUMA platforms patent, May 2016

Processor associated blocking symbol controls for serializing the accessing of data resources in a computer system
patent, April 1999

Eviction override for larx-reserved addresses
patent, April 2001

Apparatus and method for preventing cache data eviction during an atomic operation
patent, February 2002

System and method providing cache coherency and atomic memory operations in a multiprocessor computer architecture
patent, March 2002

Detecting full conditions in a queue
patent, October 2002

Multi-thread packet processor
patent-application, June 2002

Cache way prediction based on instruction base register
patent-application, September 2002

Fast and accurate cache way selection
patent-application, January 2003

Stall technique to facilitate atomicity in processor execution of helper set
patent-application, September 2004

Synchronization of parallel processes
patent-application, September 2005

Processor with cache way prediction and method thereof
patent-application, May 2006

Implementation of load linked and store conditional operations
patent-application, July 2006

Apparatus and method for sparse line write transactions
patent-application, February 2007

Separate data/coherency caches in a shared memory multiprocessor system
patent-application, July 2007

Architectural support for thread level speculative execution
patent-application, August 2007

Snoop Filter Directory Mechanism in Coherency Shared Memory System
patent-application, December 2007

Prefetch Miss Indicator for Cache Coherence Directory Misses on External Caches
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Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory
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Method and Apparatus for Employing Multi-Bit Register File Cells and SMT Thread Groups
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System and Method for Executing Nested Atomic Blocks Using Split Hardware Transactions
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