DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution

Abstract

In a multiprocessor system with at least two levels of cache, a speculative thread may run on a core processor in parallel with other threads. When the thread seeks to do a write to main memory, this access is to be written through the first level cache to the second level cache. After the write though, the corresponding line is deleted from the first level cache and/or prefetch unit, so that any further accesses to the same location in main memory have to be retrieved from the second level cache. The second level cache keeps track of multiple versions of data, where more than one speculative thread is running in parallel, while the first level cache does not have any of the versions during speculation. A switch allows choosing between modes of operation of a speculation blind first level cache.

Inventors:
;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1158923
Patent Number(s):
8838906
Application Number:
12/984,308
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
DOE Contract Number:  
B554331
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Gara, Alan, and Ohmacht, Martin. Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution. United States: N. p., 2014. Web.
Gara, Alan, & Ohmacht, Martin. Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution. United States.
Gara, Alan, and Ohmacht, Martin. Tue . "Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution". United States. https://www.osti.gov/servlets/purl/1158923.
@article{osti_1158923,
title = {Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution},
author = {Gara, Alan and Ohmacht, Martin},
abstractNote = {In a multiprocessor system with at least two levels of cache, a speculative thread may run on a core processor in parallel with other threads. When the thread seeks to do a write to main memory, this access is to be written through the first level cache to the second level cache. After the write though, the corresponding line is deleted from the first level cache and/or prefetch unit, so that any further accesses to the same location in main memory have to be retrieved from the second level cache. The second level cache keeps track of multiple versions of data, where more than one speculative thread is running in parallel, while the first level cache does not have any of the versions during speculation. A switch allows choosing between modes of operation of a speculation blind first level cache.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Sep 16 00:00:00 EDT 2014},
month = {Tue Sep 16 00:00:00 EDT 2014}
}

Works referenced in this record:

Eviction override for larx-reserved addresses
patent, April 2001


Apparatus and method for preventing cache data eviction during an atomic operation
patent, February 2002


Detecting full conditions in a queue
patent, October 2002


Information processing apparatus with cache coherency
patent, May 2003


Architectural support for thread level speculative execution
patent, March 2008


Low complexity speculative multithreading system based on unmodified microprocessor core
patent, July 2008


Context switching and synchronization
patent, June 2012


Multi-thread packet processor
patent-application, June 2002


Cache way prediction based on instruction base register
patent-application, September 2002


Using an L2 directory to facilitate speculative loads in a multiprocessor system
patent-application, December 2002


Fast and accurate cache way selection
patent-application, January 2003


Stall technique to facilitate atomicity in processor execution of helper set
patent-application, September 2004


Synchronization of parallel processes
patent-application, September 2005


System, apparatus and method for performing look-ahead lookup on predictive information in a cache memory
patent-application, February 2006


Memory controller and method for optimized read/modify/write performance
patent-application, April 2006


Transaction based shared data operations in a multiprocessor environment
patent-application, July 2006


Implementation of load linked and store conditional operations
patent-application, July 2006


Apparatus and method for sparse line write transactions
patent-application, February 2007


Thread-Shared Software Code Caches
patent-application, March 2007


Separate data/coherency caches in a shared memory multiprocessor system
patent-application, July 2007


Architectural support for thread level speculative execution
patent-application, August 2007


Snoop Filter Directory Mechanism in Coherency Shared Memory System
patent-application, December 2007


Prefetch Miss Indicator for Cache Coherence Directory Misses on External Caches
patent-application, August 2008


Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory
patent-application, December 2008


Speculative Memory Prefetch
patent-application, January 2009


System and Method for Executing Nested Atomic Blocks Using Split Hardware Transactions
patent-application, January 2009


Enabling Speculative State Information in a Cache Coherency Protocol
patent-application, March 2009


Efficient Deterministic Multiprocessing
patent-application, September 2009


Early header CRC in data response packets with variable gap count
patent-application, October 2009


Method, System and Apparatus for Reducing Memory Traffic in a Distributed Memory System
patent-application, November 2009


Methods and apparatuses for improving speculation success in processors
patent-application, May 2010


Cache control device and control method
patent-application, July 2010


Using Time Stamps to Facilitate Load Reordering
patent-application, August 2010


Multi-Domain Management of a Cache in a Processor System
patent-application, September 2010


Using Domains for Physical Address Management in a Multiprocessor System
patent-application, September 2010


Hierarchical Bloom Filters for Facilitating Concurrency Control
patent-application, December 2010


Detecting Task Complete Dependencies Using Underlying Speculative Multi-Threading Hardware
patent-application, March 2011


Store Aware Prefetching for a Datastream
patent-application, March 2011


Conditional Load Store in a Shared Cache
patent-application, May 2011


Atomic Commit Predicated on Consistency of Watches
patent-application, June 2011


Cache Spill Management Techniques
patent-application, June 2011


Physical Aliasing for Thread Level Speculation with a Speculation Blind Cache
patent-application, August 2011


Pre-Fetching for a Sibling Cache
patent-application, September 2011


Bulk Disambiguation of Speculative Threads in Multiprocessors
conference, January 2006