Method and apparatus of integrating memory stacks

Patent · Tue Mar 14 00:00:00 EDT 2023

OSTI ID:1987224

Yudanov, Dmitri; Ignatowski, Michael

A method and apparatus of integrating memory stacks includes providing a first memory die of a first memory technology and a second memory die of a second memory technology. A first logic die is in communication with the first memory die of the first memory technology, and includes a first memory controller including a first memory control function for interpreting requests in accordance with a first protocol for the first memory technology. A second logic die is in communication with the second memory die of the second memory technology and includes a second memory controller including a second memory control function for interpreting requests in accordance with a second protocol for the second memory technology. A memory operation request is received at the first or second memory controller, and the memory operation request is performed in accordance with the associated first memory protocol or the second memory protocol.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States); Advanced Micro Devices, Inc., Sunnyvale, CA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC52-07NA27344; B608045
• Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
• Patent Number(s): 11,604,754
• Application Number: 15/605,291
• OSTI ID: 1987224
• Resource Relation: Patent File Date: 05/25/2017
• Country of Publication: United States
• Language: English