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Title: FPGA-based computing system for processing data in size, weight, and power constrained environments

Patent ·
OSTI ID:1892875

Technologies that are well-suited for use in size, weight, and power (SWAP)-constrained environments are described herein. A host controller dispatches data processing instructions to hardware acceleration engines (HAEs) of one or more field programmable gate arrays (FPGAs) and further dispatches data transfer instructions to a memory controller, such that the HAEs perform processing operations on data stored in local memory devices of the HAEs in parallel with other data being transferred from external memory devices coupled to the FPGA(s) to the local memory devices.

Research Organization:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Organization:
USDOE National Nuclear Security Administration (NNSA)
DOE Contract Number:
NA0003525
Assignee:
National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
Patent Number(s):
11,314,508
Application Number:
17/163,754
OSTI ID:
1892875
Resource Relation:
Patent File Date: 02/01/2021
Country of Publication:
United States
Language:
English

References (10)

Flexible Neural Network Accelerator and Methods Therefor patent-application May 2018
Synchronization of parallel memory accesses in a dataflow circuit patent June 2013
Memory-based distributed processor architecture patent June 2021
Logic multiprocessor for FPGA implementation patent August 2007
Deep neural network processing on hardware accelerators with stacked memory patent January 2020
Method and apparatus for transferring data between two different interfaces patent August 2012
Hierarchical General Register File (GRF) for Execution Block patent-application October 2018
Common shared memory in a verification system patent November 2015
Parallelism in Serial Pipeline Processing patent-application October 2021
Storage system having an in-line hardware accelerator patent March 2021

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