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Title: Metal-based passivation-assisted plasma etching of III-v semiconductors

Patent ·
OSTI ID:1840499
; ; ; ;

According to one embodiment, a method includes performing a plasma etching process on a masked III-V semiconductor, and forming a passivation layer on etched portions of the III-V semiconductor. The passivation layer includes at least one of a group III element and/or a metal from the following: Ni, Cr, W, Mo, Pt, Pd, Mg, Ti, Zr, Hf, Y, Ta, and Sc.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344
Assignee:
Lawrence Livermore National Security, LLC (Livermore, CA)
Patent Number(s):
11,133,190
Application Number:
15/971,999
OSTI ID:
1840499
Resource Relation:
Patent File Date: 05/04/2018
Country of Publication:
United States
Language:
English

References (23)

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Compound Semiconductor Device Having a Gate Electrode and Method of Manufacturing the Same patent-application July 2015
Method of anisotropic etching of silicon patent March 2003
Influence of Ge and Si on Reactive Ion Etching of GaN in Cl2 Plasma journal January 2002
Three Dimensional Vertically structured Electronic Devices patent-application July 2017
Silicon Substrate Preparation for Selective III-V Epitaxy patent-application September 2015
Controlling the profile of high aspect ratio gratings in diamond journal March 2016
Sidewall passivation assisted by a silicon coverplate during Cl[sub 2]–H[sub 2] and HBr inductively coupled plasma etching of InP for photonic devices
  • Bouchoule, S.; Patriarche, G.; Guilet, S.
  • Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, Vol. 26, Issue 2 https://doi.org/10.1116/1.2898455
journal January 2008
Semiconductor Device and Fabrication Method Therefor, and Power Supply Apparatus patent-application July 2014
Three Dimensional Vertically Structured Electronic Devices patent-application August 2017
High-aspect-ratio inductively coupled plasma etching of InP using SiH4/Cl2: Avoiding the effect of electrode coverplate material
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journal March 2011
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Time-multiplexed, inductively coupled plasma process with separate SiCl[sub 4] and O[sub 2] steps for etching of GaAs with high selectivity
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journal January 2009
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Method for Fabricating InGaAIN Light-Emitting Diodes with a Metal Substrate patent-application June 2011
GaN High Voltage HFET with Passivation Plus Gate Dielectric Multilayer Structure patent-application May 2014
High voltage semiconductor device having a lateral channel and enhanced gate-to-drain separation patent-application June 2007

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