Majorana pair based qubits for fault tolerant quantum computing architecture using superconducting gold surface states

Moodera, Jagadeesh S.; Lee, Patrick A.; Wei, Peng; Manna, Sujit

Title: Majorana pair based qubits for fault tolerant quantum computing architecture using superconducting gold surface states

Patent · Tue Aug 24 00:00:00 EDT 2021

OSTI ID:1840374

Moodera, Jagadeesh S.; Lee, Patrick A.; Wei, Peng; Manna, Sujit

Under certain conditions, a fermion in a superconductor can separate in space into two parts known as Majorana zero modes, which are immune to decoherence from local noise sources and are attractive building blocks for quantum computers. Here we disclose a metal-based heterostructure platform to produce these Majorana zero modes which utilizes the surface states of certain metals in combination with a ferromagnetic insulator and a superconductor. This platform has the advantage of having a robust energy scale and the possibility of realizing complex circuit designs using lithographic methods. The Majorana zero modes are interrogated using planar tunnel junctions and electrostatic gates to selectively tunnel into designated pairs of Majorana zero modes. We give example of qubit designs and circuits that are particularly suitable for the metal-based heterostructures.

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Research Organization:: Massachusetts Inst. of Technology (MIT), Cambridge, MA (United States)

Sponsoring Organization:: USDOE; National Science Foundation (NSF); US Office of Naval Research (ONR)

DOE Contract Number:: DMR1207469; DMR1700137; FG02-03ER46076; N00014-13-1-0301; N00014-16-1-2657

Assignee:: Massachusetts Institute of Technology (Cambridge, MA)

Patent Number(s):: 11,100,419

Application Number:: 16/867,601

OSTI ID:: 1840374

Resource Relation:: Patent File Date: 05/06/2020

Country of Publication:: United States

Language:: English

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