Interconnect architecture for three-dimensional processing systems

Patent · Tue Apr 20 00:00:00 EDT 2021

OSTI ID:1823880

Jayasena, Nuwan S.; Eckert, Yasuko

A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC52-07NA27344; B609201
• Assignee: Advanced Micro Devices, Inc. (Santa Clara, CA)
• Patent Number(s): 10,984,838
• Application Number: 14/944,099
• OSTI ID: 1823880
• Resource Relation: Patent File Date: 11/17/2015
• Country of Publication: United States
• Language: English