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Title: System and method for obfuscation of electronic circuits

Patent ·
OSTI ID:1805586

A computer-implemented method of generating randomized electrical interconnects for an electronic circuit comprises steps of receiving a netlist of nodes of electronic components to be connected, each connection between the nodes forming an electrical interconnect; determining a list of one or more path directions for each electrical interconnect; determining a plurality of path direction distances for each electrical interconnect; generating a plurality of segments for each electrical interconnect, each segment having one path direction and a length which are selected at random; calculating a sum of the lengths of all of the segments in each path direction each time a segment is generated for each electrical interconnect; removing one path direction from the list of path directions when a first condition is met; and stopping the generating a plurality of segments for each electrical interconnect when a second condition is met.

Research Organization:
Kansas City Plant (KCP), Kansas City, MO (United States)
Sponsoring Organization:
USDOE National Nuclear Security Administration (NNSA)
DOE Contract Number:
NA0002839
Assignee:
Honeywell Federal Manufacturing & Technologies, LLC (Kansas City, MO)
Patent Number(s):
10,936,779
Application Number:
16/402,504
OSTI ID:
1805586
Resource Relation:
Patent File Date: 05/03/2019
Country of Publication:
United States
Language:
English

References (10)

Obfuscation techniques for enhancing software security patent December 2003
Automated adjustment of wire connections in computer-assisted design of circuits patent December 2015
Packaging for multi-processor shared-memory system patent April 2003
System and method for real-time transactional data obfuscation patent March 2016
Three-dimensional electronic circuit with multiple conductor layers and method for manufacturing same patent August 2000
Method and apparatus for blocking fluid and fluid vapors patent December 2002
Conformal 3D non-planar multi-layer circuitry patent February 2016
System and method for obfuscation of electronic circuits patent June 2019
Method of making a three-dimensional integrated circuit patent October 1996
Method and system for using pattern matching to process an integrated circuit design patent June 2009

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