Low Cost (CAPEX and variable): Tool design for cell and module fabrication with thin, free-standing silicon wafers
- Massachusetts Inst. of Technology (MIT), Cambridge, MA (United States)
This project aimed to develop technologies that can potentially enable free-standing thin (<80 μm) wafer in today’s manufacturing lines with high production yield, and thereby reduce capex barriers of silicon photovoltaics cells and modules. One of the major benefits is that thin wafer dramatically reduces the amount of polysilicon required. As a result, it can lead to reduction in the capital expenditures associated with polysilicon refining and wafer fabrication, which together are more than half of the total capital expenditure to manufacture Si PV module. We focused our efforts on developing the tools needed to enable high yield fabrication of wafer, cell, and module with thin silicon wafers. However, as the wafer thickness reduces, the major challenge is that wafer breakage increases significantly. Three technological areas were explored in this project to improve the production yield of the silicon wafer, namely detection of edge cracks via dark-field near-infrared (NIR) scattering; (2) wafer handling using controlled temperature profiles; (3) manufacturable low-stress cell interconnection for multiwire. First, the formation of wafer cracks in submillimeter length is one of the reasons that causes wafer breakages. Crack detection tools are needed to enable us to locate and track the wafer crack during manufacturing, so that we can improve the process to reduce initialization. The state-of-the-art crack detection technique cannot fulfill the need for measuring submillimeter edge cracks detrimental for thin wafers. The prototype developed in this project demonstrates the scanning of microcracks near wafer edges. With a semi-automatic laboratory setup, the submillimeter cracks were reliably detected near the edges in multi-Si wafers. The smallest detectable crack is 200 µm in length in slow scans; and submillimeter cracks are detected in high-throughput scans at the scan speed of >0.5 m/s, which is compatible with the inline detection of a manufacturing line at least 1 sec/wafer. This detection limit is a significant advancement in comparison to the benchmarked industrial tool. Second, wafer handling with the well-controlled temperature profile was thought to be the solution to reduce crack initiation and propagation during the manufacturing. However, without crack detection being widely adopted in production line, we did not find a strong industrial pull toward this technology. We did an initial literature survey and then diverted our efforts to the other tasks. Third, the innovation on low-stress multi-wire interconnection tackles a fundamental problem in the standard interconnection scheme. The standard over-under “zig-zag” interconnection induces a significant amount of stress into the soldering point on the cell whenever PV module is under stress, e.g., thermal cycling, transportation, and installation. Therefore, the interconnection process was re-designed in this project to allow for significant movement between adjacent solar cells, e.g., due to thermal expansion, without building up stresses on the solar cells or solder joints. The new interconnection method with the cross-connect wire also simplifies the tabbing and stringing process by replacing the standard over-under method with an off-cell interconnect from top to bottom. A manual tabbing and stringing tool for this new process was prototyped in the lab to demonstrate the fabrication of this new interconnection design. During the test with brass sheets as our “testing cells”, it was found that the mechanical cycling test only broke the interconnection after more than 50,000 cycles, which is equivalent to more than 130 years of the day-and-night thermal cycles. Lastly, throughout the project, we continuously analyzed the PV market with techno-economic analysis to identify the opportunity for thin Si adoption. Even though the drastic cost reduction has already happened in the past five years, our analysis results indicated that we can still save quite significantly in both manufacturing cost and factory capex, Particularly, in order to grow the PV manufacturing capacity to multi-terawatt level, reducing the thickness of silicon wafer is one of the most effective ways to quickly reduce factory capex, and sustain the high growth rate. The technologies developed in this project are readily available to provide some assistances in tackling the production yield problem.
- Research Organization:
- Massachusetts Inst. of Technology (MIT), Cambridge, MA (United States)
- Sponsoring Organization:
- USDOE Office of Energy Efficiency and Renewable Energy (EERE)
- DOE Contract Number:
- EE0007535
- OSTI ID:
- 1618395
- Report Number(s):
- DOE-MIT-EE0007535
- Resource Relation:
- Related Information: Luke Meyer, MS Thesis, Department of Mechanical Engineering, MassachusettsInstitute of Technology, 2018. Available: hdl.handle.net/1721.1/115651.E.M. Sachs, T. Buonassisi, S. Wieghold, Z. Liu, Systems and methods for crack detection, Utility Patent filed on Feb 08, 2019 with Application no. US62/628,896;Publication on Nov. 21, 2019 with PCT no. WO2019157271A3. Available at patents.google.com/patent/WO2019157271A3/.E.M. Sachs, T. Buonassisi, L. Meyer, Wire interconnection for solar cells, UtilityPatent filed on June 26, 2018. PCT no. WO2019005752A1. Available at https://patents.google.com/patent/WO2019005752A1/en?oq=WO2019005752A1
- Country of Publication:
- United States
- Language:
- English
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