Field programmable gate array bitstream verification

Patent · Tue Apr 16 00:00:00 EDT 2019

OSTI ID:1568209

Hamlet, Jason

Described herein are various technologies pertaining to confirming an integrity of a FPGA. A verifier circuit is placed into an FPGA bitstream to enable external verification of the FPGA configuration in real time without requiring readout of the FPGA configuration itself. Number generators are utilized to generate a key which is shared between the FPGA and an external verification component (VC). The key is utilized to configure an initial state of sequence registers respectively located on both the FPGA and the VC. When the FPGA is operating with an approved configuration, output from the sequence registers at the FPGA and the VC are the same.

• Research Organization: Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC04-94AL85000
• Assignee: National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
• Patent Number(s): 10,262,098
• Application Number: 14/927,046
• OSTI ID: 1568209
• Resource Relation: Patent File Date: 10/29/2015
• Country of Publication: United States
• Language: English

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