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Title: System and method for performing SRAM write assist

Patent ·
OSTI ID:1532132
;

A method and a system are provided for performing write assist. Write assist circuitry is initialized and voltage collapse is initiated to reduce a column supply voltage provided to a storage cell. A bitline of the storage cell is boosted to a boosted voltage level that is below a low supply voltage provided to the storage cell and data encoded by the bitline is written to the storage cell.

Research Organization:
NVIDIA Corp., Santa Clara, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B599861
Assignee:
NVIDIA Corporation (Santa Clara, CA)
Patent Number(s):
8,861,290
Application Number:
13/710,314
OSTI ID:
1532132
Resource Relation:
Patent File Date: 2012-12-10
Country of Publication:
United States
Language:
English

References (1)

Configuration Context Switcher patent-application April 2011

Cited By (6)

Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits patent July 2018
Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits patent August 2018
Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor patent December 2018
Write assist circuit integrated with leakage reduction circuit of a static random access memory for increasing the low voltage supply during write operations patent January 2017
Boost charge recycle for low-power memory patent January 2018
Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits patent April 2018

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