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Title: Transistor with elevated drain termination

Patent ·
OSTI ID:1531972

According to an exemplary implementation, a transistor includes drain finger electrodes interdigitated with source finger electrodes. The transistor also includes a current conduction path in a semiconductor substrate between the drain finger electrodes and the source finger electrodes. At least one of the drain finger electrodes has a drain finger electrode end and a drain finger electrode main body, where the drain finger electrode main body is non-coplaner with at least a portion of the drain finger electrode end. The transistor may also include a dielectric material situated between at least a portion of the drain finger electrode end and the semiconductor substrate. The dielectric material can be an increasing thickness dielectric material. The dielectric material can thus elevate the drain finger electrode end over the semiconductor substrate. Further, the drain finger electrode end can have an increased radius of curvature.

Research Organization:
Infineon Technologies Americas Corp., El Segundo, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AR0000016
Assignee:
Infineon Technologies Americas Corp. (El Segundo, CA)
Patent Number(s):
9,564,498
Application Number:
14/750,262
OSTI ID:
1531972
Resource Relation:
Patent File Date: 2015-06-25
Country of Publication:
United States
Language:
English

References (3)

High voltage MIS field effect transistor patent June 1996
Structure and Layout of a FET Prime Cell patent-application April 2006
LDMOS transistor with enhanced termination region for high breakdown voltage with low on-resistance patent-application September 2004