NEW EPICS/RTEMS IOC BASED ON ALTERA SOC AT JEFFERSON LAB
- Thomas Jefferson National Accelerator Facility (TJNAF), Newport News, VA (United States)
A new EPICS/RTEMS IOC based on the Altera System-on-Chip (SoC) FPGA is being designed at Jefferson Lab. The Altera SoC FPGA integrates a dual ARM Cortex-A9 Hard Processor System (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The embedded Altera SoC IOC has features of remote network boot via U-Boot from SD card or QSPI Flash, 1Gig Ethernet, 1GB DDR3 SDRAM on HPS, UART serial ports, and ISA bus interface. RTEMS for the ARM processor BSP were built with CEXP shell, which will dynamically load the EPICS applications at runtime. U-Boot is the primary bootloader to remotely load the kernel image into local memory from a DHCP/TFTP server over Ethernet, and automatically run RTEMS and EPICS. The first design of the SoC IOC will be compatible with Jefferson Lab’s current PC104 IOCs, which have been running in CEBAF 10 years. The next design would be mounting in a chassis and connected to a daughter card via standard HSMC connectors. This standard SoC IOC will become the next generation of low-level IOC for the accelerator controls at Jefferson Lab.
- Research Organization:
- Thomas Jefferson National Accelerator Facility (TJNAF), Newport News, VA (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC), Nuclear Physics (NP)
- DOE Contract Number:
- AC05-06OR23177
- OSTI ID:
- 1425919
- Report Number(s):
- JLAB-ACE-17-2557; DOE/OR/23177-4250
- Resource Relation:
- Conference: 16th International Conference on Accelerator and Large Experimental Physics Control Systems (ICALEPCS 2017) 08-13 Oct 2017. Barcelona, Spain
- Country of Publication:
- United States
- Language:
- English
Similar Records
PC/104 Embedded IOCs at Jefferson Lab
ETHERNET BASED EMBEDDED IOC FOR FEL CONTROL SYSTEM