Reverse Engineering Integrated Circuits Using Finite State Machine Analysis
- Pacific Northwest National Lab. (PNNL), Richland, WA (United States)
In this paper, we present a methodology for reverse engineering integrated circuits, including a mathematical verification of a scalable algorithm used to generate minimal finite state machine representations of integrated circuits.
- Research Organization:
- Pacific Northwest National Lab. (PNNL), Richland, WA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC05-76RL01830
- OSTI ID:
- 1417449
- Report Number(s):
- PNNL-25330; 830403000
- Country of Publication:
- United States
- Language:
- English
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